The present invention relates to semiconductor memories. More particularly, the invention relates to a memory with a memory cell comprising a MOS transistor connected between a bit line and a reference potential terminal and means for reading out the contents of the memory cell.
The prior art is represented by conventional read only memories (ROMs) that are classifiable into two types: (1) where an ordinary cell and a dummy cell are provided, and a difference in potential between bit lines associated with the dummy cell and the ordinary cell is detected by a differential amplifier; and (2) where no dummy cell is provided, and the bit line potential of the only cell is read out after being amplified by an inverter.
In FIG. 7, there is illustrated a conventional ROM of the first type. In the illustrated circuit diagram, there are included an ordinary cell and a dummy cell. The ordinary cell comprises a MOS transistor Mc having a source coupled to a ground potential Vss and a drain connect to an ordinary bit line. The dummy cell also comprises a MOS transistor Mdc having its source coupled to the ground potential Vss and a drain coupled to a dummy bit line.
A load resistor R1 is connected between the ordinary bit line and a power terminal having an electric potential Vdd. A load resistor R2 is connected between the dummy bit line and the power terminal. A differential amplifier AMP having one input coupled to the ordinary bit line and another input coupled to the dummy bit line effects a comparison between the electric potentials of the bit lines.
In the circuit of FIG. 7, the current driveability of the MOS transistor Mdc serving as the dummy cell normally is set to half the current driveability of the MOS transistor Mc serving as the ordinary cell. Additionally, the load resistor R2 for the dummy bit line can be set to half of the value of the load resistor R1 for the ordinary bit line.
In either case, the potential drop caused in the ordinary bit line by the flow of a current in the ordinary cell is faster than that in the dummy bit line. This is illustrated in FIG. 8 wherein there is included a graph illustrating how the various bit line potentials of the memory of FIG. 7 vary over time. Under the conditions including the sensitivity of .DELTA.V of the amplifier AMP and the time t required for inducing a potential difference .DELTA.V between the dummy bit line and the ordinary bit line, it follows that the time t is required for identifying the state of the memory cell.
In FIG. 9 there is illustrated a conventional ROM of the second type including a sense amplifier that amplifies the bit line potential via an inverter without the provision of a dummy cell. In the circuit diagram of FIG. 9, there is included an inverter In and a load resistor R connected between the ordinary bit line and the power terminal. The electric potential of the bit line is read out via the inverter In.
In FIG. 10 there is provided a graph illustrating how the potential in the bit line of the semiconductor memory of FIG. 9 varies over time. It can be appreciated that in this circuit, when a current flows in the memory cell, the time required for reading out the potential is rendered longer by the time period t needed for the bit-line potential to traverse the threshold voltage of the inverter In after initiation of its change.
There exists a great demand for increasing the read out speed of a semiconductor memory such as a ROM. However, it has been difficult heretofore to completely meet such demand by either of the circuits described in FIGS. 7 and 9.
In the circuit of FIG. 7, instead of a direct detection of the rapid potential change in the ordinary bit line current flow through in the cell, there is executed a detection of the potential difference between the ordinary bit line and the dummy bit line where the potential change in speed is as low as half the value in the ordinary bit line, so that the time required for reading out such potential change is rendered twice that as is the case of direct detection, should the sensitivity of the amplifiers be the same.
In the circuit of FIG. 9, a considerable amount of time is needed to execute a memory read out.